Random Testing of Asynchronous VLSI Circuits

Figure 4.1: Improving VLSI testability using (a) demultiplexers; (b) multi-Abstract Asynchronous VLSI designs are becoming an intensive area of research due to their advantages in comparison with synchronous circuits, such as the absence of the clock distribution problem, lower power consumption and higher performance. The work described in this thesis is an attempt to find possible ways to test asynchro-nous VLSI circuits using random (or, more accurately, pseudo-random) patterns. The main results have been obtained in the field of random testing of stuck-at faults in micro-pipelines. An asynchronous random testing interface has been designed which includes an asyn-chronous pseudo-random pattern generator and an asynchronous parallel signature ana-lyser. A program model of the universal pseudo-random pattern generator has been developed. The universal pseudo-random pattern generator can produce multi-bit pseudo-random sequences without an obvious shift operation and it can also produce weighted pseudo-random test patterns. Mathematical expressions have been derived for predicting the test length for random pattern testing of logic blocks of micropipelines by applying equiprobable and weighted random patterns to the inputs. The probabilistic properties of the n-input Muller-C element have been investigated. It is shown that the optimal random test procedure for the n-input Muller-C element is random testing using equiprobable input signals. Using the probabilistic properties of the Muller-C element and multiplexers incorporated into the circuit a certain class of asyn-chronous networks can be designed for random pattern testability. It is also shown how it is possible to produce pseudo-random patterns to detect all stuck-at faults in micropi-pelines. No portion of the work referred to in this thesis has been submitted in support of an application for another degree or qualification of this or any other university or institute of learning. Copyright in text of this thesis rests with the Author. Copies (by any process) either in full, or of extracts, may be made only in accordance with instructions given by the Author and lodged in the John Rylands University Library of Manchester. Details may be obtained from the Librarian. This page must form part of any such copies made. Further copies (by any process) of copies made in accordance with such instructions may not be made without the permission (in writing) of the Author. The ownership of any intellectual property rights which may be described in this thesis is vested in the University of Manchester, subject to any prior agreements to the contrary , and may not …